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Work Experience
Silicon Engineer Intern
Microsoft• May 2022 - Present
- Formulate and customize a Python automation flow that estimates any silicon module’s idle power by analyzing its RTL file, reducing the engineering time needed to obtain such figures by 90%. - Analyze PrimePower reports to verify clock gating, a power-saving measure, on over 30 design blocks and iterate with RTL engineers to reduce the power consumption of specific registers
Software Engineer Intern
Intel Corporation• May 2020 - September 2021
- Simplified clock-domain-crossing (CDC) debugging by 75% by designing a timing report that classifies 15 types of CDCs using rules which detect standard topologies such as handshake buses, checks CDCs for safe practices recommended by application engineers, and provides correction suggestions for unsafe topologies - Invented the clock network report, which reveals a design’s hierarchical clock paths and clock reconvergences by performing memoized traversal on the internal timing graph with pruning based on user inputs - Obtained Tcl API knowledge by implementing over 10 Tcl commands using C++ backend, such as a command that returns the clocks driving a node in the design, which saw 5x speed-up compared with a pure Tcl implementation
Education
University of Toronto, Toronto
Chemical Engineering, BE• September 2018 - Present
GPA 3.97/4.00, Dean's List, Top ECE Student. Graduating in May 2023