Venkatesh Rajagopalan
@server_monk
Verilog Virtuoso
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Work Experience
Project Intern
Texas Instruments•  January 2022 - June 2022•  Bangalore, India
Developed algorithm to reduce third-order harmonic distortion in ADCs by employing a randomized ±1 dither signal, resulting in improved accuracy and fidelity of signal processing. Implemented a corrector block utilizing an accumulator feedback network to effectively average distortion samples, improving overall system performance. Achieved a 90.06% reduction in third-order harmonic distortions through advanced data analysis and scripting in Python, demonstrating significant optimization.
Education
North Carolina State University, Raleigh
Electrical Engineering & Computer Science, MS•  August 2023 - Present•  GPA: 3.72
BITS, Hyderabad (Birla Institute of Technology & Science)
Electrical Engineering, BE•  August 2018 - August 2022•  CGPA: 8.32
